How do network switches work?

Apologies if this is off-topic for this group, but I'm not sure where
else to ask it:

I'm wondering how network switches work. Layer 3 routing makes a lot
of sense to me, but I'm still pretty fuzzy on what exactly goes on at
layers 1 and 2. My 8-port Netgear RO318 router has a Broadcom 5317
8-port switch-on-a-chip. There is only *one* ethernet controller in
the device, and its integrated into the CPU. In my newer Netgear
WGT634U linux-based router, the switch, CPU, and ethernet controller
are all integrated into one IC.

My understanding is that in these unmanaged switches, the switching is
basically done by an ASIC that inspects the destination MAC address of
each packet and looks it up in a table of MAC<->port mappings. Does
each ethernet port on the switch have its own MAC and PHY, integrated
into the switch-on-a-chip IC? How does the switch build the table
associating MAC addresses to ports? Is there a limit to the size of
the table if there is a large hub-connected LAN segment on each port?

How do managed switches work? Is the switching still done by an ASIC,
or is it done by a general-purpose CPU such as in a home router?

Thanks for anyone who can clear up these confusions for me!

Dan Lenski
University of Maryland

(E-Mail Removed) wrote:

> Apologies if this is off-topic for this group, but I'm not sure where
> else to ask it:

You really should try google first. A quick google search on "how network
switches work" yields

http://computer.howstuffworks.com/lan-switch.htm

If that does not work for you, there are many other links listed in the
google search.



--
Still waiting for a rational answer from Bittwister to this:
<nfqlo3-(E-Mail Removed)>.

left_coast wrote:
> (E-Mail Removed) wrote:
>
> > Apologies if this is off-topic for this group, but I'm not sure where
> > else to ask it:
>
> You really should try google first. A quick google search on "how network
> switches work" yields
>
> http://computer.howstuffworks.com/lan-switch.htm
>
> If that does not work for you, there are many other links listed in the
> google search.

Thanks for that link. This one from Cisco is what I read first and is
pretty good:
http://www.ciscopress.com/articles/a...&seqNum=4&rl=1

I already understand how switching works in terms of what parts of the
packet are being inspected, and the difference between cut-through and
store-and-forward. But what I don't really understand are the gritty
details of HOW the switch does what it does: does it happen with a
custom ASIC or is it basically done in software like a router?

If I wanted to build a router, I'd get a computer with a couple of
ethernet cards, put linux on it, and start playing with Netfilter and
route.

But if I wanted to build a switch... how would I do that? Do the
individual ports on a switch have their own individual Ethernet
controllers? Is the brain of the switch an ASIC or a general-purpose
CPU?

Dan

(E-Mail Removed) wrote:

> If I wanted to build a router, I'd get a computer with a couple of
> ethernet cards, put linux on it, and start playing with Netfilter and
> route.

A router is not a switch.

--
Still waiting for a rational answer from Bittwister to this:
<nfqlo3-(E-Mail Removed)>.

left_coast wrote:
> (E-Mail Removed) wrote:
>
> > If I wanted to build a router, I'd get a computer with a couple of
> > ethernet cards, put linux on it, and start playing with Netfilter and
> > route.
>
> A router is not a switch.

I couldn't agree more :-)

Now, I understand the combination of hardware and software typically
used to *implement* the behavior of a router in an efficient manner.

However, the hardware and software used to implement a switch remains a
mystery to me, and that's what I'm asking about.

Dan

(E-Mail Removed) writes:

> My understanding is that in these unmanaged switches, the switching is
> basically done by an ASIC that inspects the destination MAC address of
> each packet and looks it up in a table of MAC<->port mappings. Does
> each ethernet port on the switch have its own MAC and PHY, integrated
> into the switch-on-a-chip IC?

Yes.

One of my friends works at a place where they design those chips. I've
seen an 8 port 10 Gpbs switch on a chip no bigger than the CPU in you
computer. That's kind of cool, if you ask me :-)

> How does the switch build the table associating MAC addresses to
> ports?

Normally by flooding.

> Is there a limit to the size of the table if there is a large
> hub-connected LAN segment on each port?

Yes, it normally says what the limit is in the manual for your switch.
It's typically 2-8.000 entries for smaller switches destined for home
networks.

> How do managed switches work? Is the switching still done by an ASIC,
> or is it done by a general-purpose CPU such as in a home router?

Normally the switching happens in a dedicated ASIC and the management
functionality happens in a general purpose CPU. In some switches more
advanced features are also run on the general purpose CPU which
usually gives a huge performance hit.

> Thanks for anyone who can clear up these confusions for me!

I hope this helps, otherwise you'll just have to ask again :-)

--
Jacob

Thanks for the info, Jacob! That's exactly what I'm looking for.

Jacob Bunk Nielsen wrote:
> Yes.
>
> One of my friends works at a place where they design those chips. I've
> seen an 8 port 10 Gpbs switch on a chip no bigger than the CPU in you
> computer. That's kind of cool, if you ask me :-)

Yes, very cool indeed. 8 port 10 Gbps is incredible... that's about 5
million packets a second if each port is saturated. It seems like the
main road block to wire-speed switching would be the core logic
responsible for deciding which port each packet goes to. Assuming
there's only one such core, only one packet could be redirected at a
time, although the Ethernet transceivers could of course physically
send and receive other packets at the same time.

Are there any companies that actually release data sheets on these
things? Broadcom is positively secret about their ICs it seems: I
can't find anything more than a 2-page brief on any of their
switch-on-a-chip products.

> Normally the switching happens in a dedicated ASIC and the management
> functionality happens in a general purpose CPU. In some switches more
> advanced features are also run on the general purpose CPU which
> usually gives a huge performance hit.

Interesting... so if the ASIC doesn't know how to handle a packet, it
punts it to the CPU? Do you know of any well-documented switch chips
that have this management interface?

Dan

Thanks for the info, Jacob! That's exactly what I'm looking for.

Jacob Bunk Nielsen wrote:
> Yes.
>
> One of my friends works at a place where they design those chips. I've
> seen an 8 port 10 Gpbs switch on a chip no bigger than the CPU in you
> computer. That's kind of cool, if you ask me :-)

Yes, very cool indeed. 8 port 10 Gbps is incredible... that's about 5
million packets a second if each port is saturated. It seems like the
main road block to wire-speed switching would be the core logic
responsible for deciding which port each packet goes to. Assuming
there's only one such core, only one packet could be redirected at a
time, although the Ethernet transceivers could of course physically
send and receive other packets at the same time.

Are there any companies that actually release data sheets on these
things? Broadcom is positively secret about their ICs it seems: I
can't find anything more than a 2-page brief on any of their
switch-on-a-chip products.

> Normally the switching happens in a dedicated ASIC and the management
> functionality happens in a general purpose CPU. In some switches more
> advanced features are also run on the general purpose CPU which
> usually gives a huge performance hit.

Interesting... so if the ASIC doesn't know how to handle a packet, it
punts it to the CPU? Do you know of any well-documented switch chips
that have this management interface?

Dan

(E-Mail Removed) writes:
> Jacob Bunk Nielsen wrote:
>
>> One of my friends works at a place where they design those chips. I've
>> seen an 8 port 10 Gpbs switch on a chip no bigger than the CPU in you
>> computer. That's kind of cool, if you ask me :-)
>
> Yes, very cool indeed. 8 port 10 Gbps is incredible... that's about 5
> million packets a second if each port is saturated. It seems like the
> main road block to wire-speed switching would be the core logic
> responsible for deciding which port each packet goes to. Assuming
> there's only one such core, only one packet could be redirected at a
> time, although the Ethernet transceivers could of course physically
> send and receive other packets at the same time.

Don't worry, I'm sure they can handle more than one frame at a time in
such a switch fabric.

I'm not a hardware guy, so I don't know a lot about the specifics. I
did however read a couple of interesting articles about the nature of
switch fabrics a while ago. Of course I can't remember where I found
them. Sorry.

> Are there any companies that actually release data sheets on these
> things? Broadcom is positively secret about their ICs it seems: I
> can't find anything more than a 2-page brief on any of their
> switch-on-a-chip products.

Try to see what you can find at
<http://www.vitesse.com/technologies/index.php?id=7>. I don't know if
it's worth anything to you, but you can always have a look.

>> Normally the switching happens in a dedicated ASIC and the management
>> functionality happens in a general purpose CPU. In some switches more
>> advanced features are also run on the general purpose CPU which
>> usually gives a huge performance hit.
>
> Interesting... so if the ASIC doesn't know how to handle a packet, it
> punts it to the CPU? Do you know of any well-documented switch chips
> that have this management interface?

No, as I said I'm not really a hardware guy. But try to browse
documentation at cisco.com and look for features on their switches
that has huge performance-hits. That's usually because they are
handled in software rather than in dedicated hardware. It's often L3
and L4 features on a devices that's mainly targeted at the L2 market.

--
Jacob